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タイトル: Design techniques for switched capacitor adaptive line equlizer
著者: Nakayama, Kenji link image
Sato, Yayoi
Kuraishi, Yoshiaki
中山, 謙二
発行日: 1985年 8月
出版社(者): Institute of Electrical and Electronics Engineers (IEEE)
引用: IEEE transactions on circuits and systems CAS-32 (8), pp. 759-766
雑誌名: IEEE transactions on circuits and systems
ISSN: 0098-4094
巻: CAS-32
号: 8
開始ページ: 759
終了ページ: 766
抄録: Design techniques are described for a switched capacitor adaptive line equalizer which is applied to high-speed (200 kb/s) digital transmission over analog subscriber loops. An equalizer transfer function is approximated so as to minimize intersymbol interference of an isolated pulse response. Optimum pole-zero location, which is suited to line characteristics in a wide frequency band, is also discussed. In order to attain high accuracy capacitor ratios using a small unit capacitor, capacitor values are rounded off into equivalent integer values, and are discretely optimized using pole-zero deviation as an error criterion. The equalizer has a finite number of frequency responses which correspond to line lengths. Gain and delay time differences between the adjoining step responses are compressed. The switched capacitor line equalizer was fabricated using 3- mu m CMOS technology. Measured data were very close to designed performances.
URI: http://hdl.handle.net/2297/3948
資料種別: Journal Article
版表示: publisher

このアイテムを引用あるいはリンクする場合は次の識別子を使用してください。 http://hdl.handle.net/2297/3948



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